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1/32 product preview may 2001 this is preliminary information on a new product now in development. details are subject to change without notice. m25p40 4 mbit, low voltage, serial flash memory with 20 mhz spi bus interface features summary n 4 mbit of flash memory n page program (up to 256 bytes) in 2 ms (typical) n sector erase (512 kbit) in 2 s (typical) n bulk erase (4 mbit) in 8 s (typical) n 2.7 v to 3.6 v single supply voltage n spi bus compatible serial interface n 20 mhz clock rate (maximum) n deep power-down mode 1 m a (typical) n electronic signature n more than 100,000 erase/program cycles per sector n more than 20 year data retention figure 1. packages so8 (mn) 150 mil width 8 1 so8 (mw) 200 mil width 8 1
m25p40 2/32 summary description the m25p40 is a 4 mbit (512k x 8) serial flash memory, with advanced write protection mecha- nisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 8 sectors, each con- taining 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as con- sisting of 2048 pages, or 524,288 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. figure 2. logic diagram figure 3. so connections table 1. signal names ai04090 s v cc m25p40 hold v ss w q c d 1 ai04091 2 3 4 8 7 6 5d v ss c hold q sv cc w m25p40 c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
3/32 m25p40 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be pro- grammed. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal read, program, erase or write status register cycle is in progress, the device will be in the standby mode (this is not the deep power-down mode). driving chip select (s) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (s) is required prior to the start of any instruction. hold (hold). the hold (hold) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. to start the hold condition, the device must be se- lected, with chip select (s) driven low. write protect (w). the main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register).
m25p40 4/32 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 5, is the clock polarity when the bus mas- ter is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus note: 1. the write protect (w) and hold (hold) signals should be driven, high or low as appropriate. figure 5. spi modes supported ai03746c bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold ai01438 c c msb lsb cpha dorq 0 1 cpol 0 1
5/32 m25p40 operating features page programming to program one data byte, two instructions are re- quired: write enable (wren), which is one byte, and a page program (pp) sequence, which con- sists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be pro- grammed at a time (changing bits from 1 to 0), pro- vided that they lie in consecutive addresses on the same page of memory. sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. polling during a program cycle or erase cycle a further improvement in the programming time or erase time can be achieved by not waiting for the worst case delay (t w ,t pp ,t se ,ort be ). the write in progress (wip) bit is provided in the status regis- ter so that the application program can monitor its value, polling it to establish when the previous pro- gram cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select (s) is low, the device is en- abled, and in the active power mode. when chip select (s) is high, the device is dis- abled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device re- mains in this mode until another specific instruc- tion (the release from deep power-down mode and read electronic signature (res) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertant write, program or erase instructions. status register the status register contains a number of status and control bits that can be read or set (as appro- priate) by specific instructions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits. table 2. status register format note: 1. srwd, bp2, bp1 and bp0 are non-volatile read and write bits. 2. wel and wip are volatile read-only bits (wel is set and reset by specific instructions; wip is automatically set and reset by the internal logic of the device). b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip
m25p40 6/32 protection modes non-volatile memory devices can be used in envi- ronments that are particularly noisy, and within ap- plications that could experience problems if memory bytes are corrupted. consequently, the device features the following data protection mechanisms: n power-on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. n program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. n all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit . this bit is returned to its reset state by the following events: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion page program (pp) instruction completion sector erase (se) instruction completion bulk erase (be) instruction completion n the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). n the write protect (w) signal allows the block protect (bp2, bp1, bp0) bits to be protected. this is the hardware protected mode (hpm). n in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertant write, program and erase instructions while the device is not in active use. for example, after downloading a block of code from the device to ram, the bus master can put the device in deep power-down mode until it is next needed, thereby saving power and reduc- ing the risk of data corruption. table 3. protected area sizes note: 1. the device is ready to accept a bulk erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0. status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none whole memory 1 (sectors 0 to 7) 0 0 1 upper eighth (sector 7) lower seven-eighth (sectors 0 to 6) 0 1 0 upper quarter (sectors 6 and 7) lower three-quarters (sectors 0 to 5) 0 1 1 upper half (sectors 4 to 7) lower half (sectors 0 to 3) 1 0 0 whole memory (sectors 0 to 7) none 1 0 1 whole memory (sectors 0 to 7) none 1 1 0 whole memory (sectors 0 to 7) none 1 1 1 whole memory (sectors 0 to 7) none
7/32 m25p40 hold condition the hold (hold) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. to enter the hold condition, the device must be selected, with chip select (s) low. the hold condition starts on the falling edge of the hold (hold) signal, provided that this coincides with serial clock (c) being low (as shown in fig- ure 6). the hold condition ends on the rising edge of the hold (hold) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts when serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends when se- rial clock (c) next goes low. (this is shown in fig- ure 6). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. normally, the device is kept selected, with chip select (s) driven low, for the whole duration of the hold condition. if chip select (s) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. the memory re- mains in the hold condition as long as hold (hold) is low. to restart communication with the device, it is necessary both to drive hold (hold) high, and to drive chip select (s) low. figure 6. hold condition activation electronic signature the device features an 8-bit electronic signature. its value is 12h. it can be read using the release from deep power-down and read electronic sig- nature (res) instruction. ai02029b hold pin clock active memory status hold active hold active
m25p40 8/32 memory organization the memory is organized as: n 524,288 bytes (8 bits each) n 8 sectors (512 kbits, 65536 bytes each) n 2048 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. table 4. memory organization sector address range 7 70000h 7ffffh 6 60000h 6ffffh 5 50000h 5ffffh 4 40000h 4ffffh 3 30000h 3ffffh 2 20000h 2ffffh 1 10000h 1ffffh 0 00000h 0ffffh
9/32 m25p40 figure 7. block diagram ai04092 hold s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder size of the read-only memory area c d q status register 00000h 7ffffh 000ffh
m25p40 10/32 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 5. depending on the instruction, the one-byte in- struction code is followed by address bytes, or by data bytes, or by both or none. chip select (s) must be driven high after the last bit of the instruc- tion sequence has been shifted in. at the end of a page program (pp), sector erase (se), bulk erase (be) or write status register (wrsr) instruction, chip select (s) must be driv- en high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s) must driven high when the number of clock pulses after chip select (s) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cy- cle continues unaffected. table 5. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 0 0 0 wrdi write disable 0000 0100 0 0 0 rdsr read status register 0000 0101 0 0 1 to wrsr write status register 0000 0001 0 0 1 read read data bytes 0000 0011 3 0 1 to pp page program 0000 0010 3 0 1 to 256 se sector erase 1101 1000 3 0 0 be bulk erase 1100 0111 0 0 0 dp deep power-down 1011 1001 0 0 0 res release from deep power-down, and read electronic signature 1010 1011 031to release from deep power-down 0 0 0
11/32 m25p40 write enable (wren) the write enable (wren) instruction (figure 8) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set pri- or to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s) low, sending the in- struction code, and then driving chip select (s) high. figure 8. write enable (wren) sequence write disable (wrdi) the write disable (wrdi) instruction (figure 9) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s) low, sending the instruc- tion code, and then driving chip select (s) high. the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction com- pletion page program (pp) instruction completion sector erase (se) instruction completion bulk erase (be) instruction completion figure 9. write disable (wrdi) sequence c d ai02281d s q 2 1 34567 high impedance 0 instruction c d ai03750c s q 2 1 34567 high impedance 0 instruction
m25p40 12/32 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status reg- ister continuously, as shown in figure 10. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) in- struction. when one or both of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant mem- ory area (as defined in table 3) becomes protect- ed against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hard- ware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, both block protect (bp2, bp1, bp0) bits are 0. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 10. read status register (rdsr) sequence write status register (wrsr) the write status register (wrsr) instruction al- lows new values to be written to the status regis- ter. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 11. the write status register (wrsr) instruction has no effect on b6, b5, b1 and b0 of the status reg- ister. b6 and b5 are always read as 0. chip select (s) must be driven high after the eighth bit of the data byte has been latched in. if c d s 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction 0 ai02031c q 76543210 status register out high impedance msb 76543210 status register out msb 7
13/32 m25p40 not, the write status register (wrsr) instruction is not executed. as soon as chip select (s) is driv- en high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction al- lows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as de- fined in table 3. the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w) signal. the status register write disable (srwd) bit and write protect (w) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not execut- ed once the hardware protected mode (hpm) is entered. figure 11. write status register (wrsr) sequence the protection features of the device are summa- rized in table 6. when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in- struction, regardless of the whether write protect (w) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w): if write protect (w) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w) is driven low, it is not pos- sible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are re- jected, and are not accepted for execution). as a consequence, all the data bytes in the memo- ry area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disable (srwd) bit after driving write protect (w) low or by driving write protect (w) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w) high. if write protect (w) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. c d ai02282c s q 2 1 3 4 5 6 7 8 9 101112131415 high impedance instruction status register in 0 765432 0 1 msb
m25p40 14/32 table 6. protection modes note: 1. as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 3. read data bytes (read) the device is first selected by driving chip select (s) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the mem- ory contents, at that address, is shifted out on se- rial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 12. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is termi- nated by driving chip select (s) high. chip select (s) can be driven high at any time during data out- put. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data bytes (read) sequence note: 1. address bits a23 to a19 are don't care. w signal srwd bit mode write protection of the status register memory content protected area 1 unprotected area 1 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the bp2, bp1 and bp0 bits can be changed protected against page program and sector erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the bp2, bp1 and bp0 bits cannot be changed protected against page program and sector erase ready to accept page program and sector erase instructions c d ai03748c s q 23 2 1 3 4 5 6 7 8 9 10 2829303132333435 22 21 3 2 1 0 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
15/32 m25p40 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the page program (pp) instruction is entered by driving chip select (s) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a6-a0) are not all zero, all transmitted data exceeding the ad- dressed page boundary roll over, and are pro- grammed from the start address of the same page (the one whose 8 least significant address bits (a6-a0) are all zero). chip select (s) must be driv- en low for the entire duration of the sequence. the instruction sequence is shown in figure 13. if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without hav- ing any effects on the other bytes of the same page. chip select (s) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s) is driven high, the self- timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page program cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see tables 4 and 3) is not executed. figure 13. page program (pp) sequence note: 1. address bits a23 to a19 are don't care. c d ai04082 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 3 4 5 6 7 8 9 10 2829303132333435 22 21 3 2 1 0 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
m25p40 16/32 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decod- ed, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the sector (see table 4) is a valid address for the sector erase (se) instruction. chip select (s) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14. chip select (s) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cy- cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see tables 4 and 3) is not executed. figure 14. sector erase (se) sequence note: 1. address bits a23 to a19 are don't care. 24 bit address c d ai03751c s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
17/32 m25p40 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the bulk erase (be) instruction is entered by driv- ing chip select (s) low, followed by the instruction code on serial data input (d). chip select (s) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15. chip select (s) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not exe- cuted. as soon as chip select (s) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed bulk erase cycle, and is 0 when it is com- pleted. when the cycle is completed, the write en- able latch (wel) bit is reset. the bulk erase (be) instruction is executed only if both block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 15. bulk erase (be) sequence c d ai03752c s 2 1 34567 0 instruction
m25p40 18/32 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 13). once the device has entered the deep power- down mode, all instructions are ignored except the release from deep power-down and read elec- tronic signature (res) instruction. this releases the device from this mode. the release from deep power-down and read electronic signature (res) instruction also allows the electronic signa- ture of the device to be output on serial data out- put (q). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (s) low, followed by the in- struction code on serial data input (d). chip se- lect (s) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16. chip select (s) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruc- tion is not executed. as soon as chip select (s) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 16. deep power-down (dp) sequence c d ai03753c s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
19/32 m25p40 release from deep power-down and read electronic signature (res) once the device has entered the deep power- down mode, all instructions are ignored except the release from deep power-down and read elec- tronic signature (res) instruction. executing this instruction takes the device out of the deep pow- er-down mode. the instruction can also be used to read, on serial data output (q), the 8-bit electron- ic signature of the device. except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (res) instruction always provides access to the electronic signature of the device, and can be ap- plied even if the deep power-down mode has not been entered. any release from deep power-down and read electronic signature (res) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s) low. the instruction code is followed by a dummy 3-byte address (a23-a0), each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 17. the release from deep power-down and read electronic signature (res) instruction is terminat- ed by driving chip select (s) high after the elec- tronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select (s) is driven low, cause the electronic signature to be output repeatedly. when chip select (s) is driven high, the device is put in the standby mode after a delay of t res2 . the device waits to be selected, so that it can receive, decode and execute instructions. figure 17. release from deep power-down and read electronic signature (res) sequence c d ai04047b s q 23 2 1 3 4 5 6 7 8 9 10 2829303132333435 22 21 3 2 1 0 36 37 38 765432 0 1 high impedance electronic signature out instruction 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2
m25p40 20/32 driving chip select (s) high after the 8 - bit instruc- tion byte has been received by the device, but be- fore the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in fig- ure 18), still insures that the device is taken out of the deep power-down mode, but incurs a delay (t res1 ) before the device is put in standby mode. chip select (s) must remain high for at least t res1 (max), as specified in table 9. figure 18. release from deep power-down (res) sequence c d ai04078 s 2 1 34567 0 t res1 stand-by mode deep power-down mode q high impedance instruction
21/32 m25p40 power-up, power-down and delivery state power-up in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are disabled the device will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. when the power supply is turned on, v cc rises from v ss to v cc (min), passing through a value v wi in between. the device ignores all page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: t puw after v cc passed the v wi threshold v cc passed the v cc (min) level these values are specified in table 7. at power-up, the device must not be selected (that is chip select (s) must follow the voltage supplied on v cc ) until the supply voltage reaches v cc (min). once v cc has reached v cc (min), chip select (s) must remain high for a time greater than t vsl (min) (as specified in table 7). after a power-up, the device is in the following state: the device is in the standby mode (not the deep power-down mode). the write enable latch (wel) bit is reset. power-down at power-up and power-down, the device must not be selected (that is chip select (s) must follow the voltage applied on v cc ) until v cc reaches the correct value: v cc (min) at power-up v ss at power-down a simple pull-up resistor on chip select (s) can be used to insure safe and proper power-up and power-down. table 7. power-up timing and v wi threshold note: 1. these parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). table 8. initial status register format symbol parameter min. max. unit t vsl 1 v cc (min) to s low 10 m s t puw 1 time delay to write instruction 15 ms v wi 1 write inhibit voltage 1.5 2.5 v b7 b0 0 0000000
m25p40 22/32 maximum rating stressing the device above the rating listed in the absolute maximum ratingso table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 9. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature 65 150 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (with respect to ground) 0.3 4.0 v v cc supply voltage 0.6 4.0 v v esd electrostatic discharge voltage (human body model) 2 2000 2000 v
23/32 m25p40 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 10. operating conditions table 11. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 19. ac measurement i/o waveform table 12. capacitance note: sampled only, not 100% tested, at t a =25 c and a frequency of 20 mhz. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature 40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter test condition min . max . unit c out output capacitance (q) v out =0v 8 pf c in input capacitance (other pins) v in =0v 6 pf
m25p40 24/32 table 13. dc characteristics symbol parameter test conditio n (in addition to those in table 10) min. max. unit i li input leakage current 2 m a i lo output leakage current 2 m a i cc1 standby current s=v cc ,v in =v ss or v cc 50 m a i cc2 deep power-down current s = v cc ,v in =v ss or v cc 5 m a i cc3 operating current (read) c = 0.1v cc / 0.9.v cc at 20 mhz, q = open 3ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage 0.6 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = 100 m av cc 0.2 v
25/32 m25p40 table 14. ac characteristics note: 1. t ch +t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. test condition s specified in table 10 and table 11 symbol alt. parameter min. typ. max. unit f c f c clock frequency for all instructions d.c. 20 mhz t slch t css s active setup time (relative to c) 15 ns t chsl s not active hold time (relative to c) 10 ns t ch 1 t clh clock high time 22 ns t cl 1 t cll clock low time 22 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 10 ns t shch s not active setup time (relative to c) 10 ns t shsl t csh s deselect time 100 ns t shqz 2 t dis output disable time 20 ns t clqv t v clock low to output valid 20 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 10 ns t chhh hold hold time (relative to c) 10 ns t hhch hold setup time (relative to c) 10 ns t chhl hold hold time (relative to c) 10 ns t hhqx 2 t lz hold to output low-z 20 ns t hlqz 2 t hz hold to output high-z 20 ns t dp 2 s high to deep power-down mode 3 m s t res1 2 s high to standby mode without electronic signature read 3 m s t res2 2 s high to standby mode with electronic signature read 1.8 m s t w write status register cycle time 3 5 ms t pp page program cycle time 2 5 ms t se sector erase cycle time 2 3 s t be bulk erase cycle time 8 12 s
m25p40 26/32 figure 20. serial input timing figure 21. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz
27/32 m25p40 figure 22. output timing c q ai01449c s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv
m25p40 28/32 package mechanical so8 narrow 8 lead plastic small outline, 150 mils body width note: drawing is not to scale. so8 narrow 8 lead plastic small outline, 150 mils body width so-a e n cp b e a d c l a1 a 1 h hx45 symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
29/32 m25p40 so8 wide 8 lead plastic small outline, 200 mils body width note: drawing is not to scale. so8 wide 8 lead plastic small outline, 200 mils body width so-b e n cp b e a2 d c l a1 a h a 1 symb. mm inches typ. min. max. typ. min. max. a 2.03 0.080 a1 0.10 0.25 0.004 0.010 a2 1.78 0.070 b 0.35 0.45 0.014 0.018 c 0.20 0.008 d 5.15 5.35 0.203 0.211 e 5.20 5.40 0.205 0.213 e 1.27 0.050 h 7.70 8.10 0.303 0.319 l 0.50 0.80 0.020 0.031 a 0 10 0 10 n8 8 cp 0.10 0.004
m25p40 30/32 part numbering table 15. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m25p40 v mn 6 t device type m25p device function 40 = 4 mbit (512k x 8) operating voltage v=v cc = 2.7 to 3.6v package mn = so8 (150 mil width) mw = so8 (200 mil width) temperature range 6=40to85 c optio n t = tape & reel packing
31/32 m25p40 revision history table 16. document revision history date rev. description of revision 12-apr-2001 1.0 document written 25-may-2001 1.1 serial paged flash memory renamed as serial flash memory
m25p40 32/32 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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